79th EAGE Conference & Exhibition 2017
Energy, Technology, Sustainability - Time to open a new Chapter
Workshop 15: Programming on Modern HPC Architectures - Efficiency and Portability
|WS15||Friday 16 June|
|Title:||Programming on Modern HPC Architectures - Efficiency and Portability|
|Convenors:||N. Bienati (Eni)
G. Crouse (Society of HPC Professionals)
J. Thorbecke (Cray Inc.)
In this workshop we will discuss shortcomings and experiences with of the current programming languages and introduce new, better suited, programming techniques. Alternative solutions to the de-facto standard (CAF, Chapel, TBB, ...) are of interest as well. The goal of the workshop is to get insight what the current bottlenecks are to write maintainable, portable, fault tolerant, and good performing code.
The current age of accelerated/many-core computing requires different programming skills and languages. Modern HPC architectures have many levels of parallelisation. For example each programmer has to deal with vectorisation, multi-threading, multi-core, and multi-node.
C/C++/Fortran are not designed to program these hybrid many-core architectures. At the moment an accelerator-language (Cuda, OpenMP/ACC/CL) combined with MPI is the de-facto standard. New languages (and better compilers) can help programmers to make better use of modern hardware and write maintainable, portable and good performing programs.
Given the many different efficient languages for different architectures the importance of writing “maintainable, portable and good performing programs” with existing languages has grown.
The subtopics addressed are:
1) Bottlenecks in current HPC software stack
- Shortcomings of current programming languages.
2) New languages better suited for HPC hardware
- Can new languages be the solution to program for heterogeneous hardware?
- Development of compilers and directives.
- What characteristics should a new programming language have to overcome current problems?
3) Getting ready for Exascale
- What to expect from future exascale architectures
- How to run on exascale systems
4) Maintain and porting existing codes
-What is the trade-off between maintainability/portability vs performance? which of the two sides is impacting (or perceived to be impacting) TCO of hw+sw more?
- Considered all the different alternatives in terms of hw solutions (KNL, GPUs, FPGAs) and programming models (Cuda, OpenMP/ACC/CL), which sw engineering principles and practices O&G industry is using to preserve/enforce sw maintainability/portability?
- What are the tools and approaches that we are borrowing or could borrow from other industries?
-In light of such complexities, how do we measure the value of our custom sw?
|09:00||Welcome and intro|
|09:15|| Cost-effective Algorithm Prototyping for HPC-environments with Continuous Resource Profiling
P. Mazzucchelli* (Aresys), M. Codazzi (Aresys)
|09:40|| ALOMA - An Auto-Parallelization Tool for Seismic Processing
D. Merten* (Fraunhofer ITWM), F. Preundt (Fraunhofer ITWM)
|10:05||Devito - Generation of High-performance Code from Symbolic Finite-difference for Geophysical Exploration
F. Luporini* (Imperial College)
|11:20||Chapel - A Programming Language for Productive Parallel Computing
B. Chamberlain* (Cray)
|11:45||The Python Programming Language for HPC in the Geosciences - An overview
F. Broggini* (ETH Zürich), L. Krischer (Munich University)
|12:10||Modern HPC Programming - Parts New, Old, and Borrowed
B. Long* (Cray)
|13:45||Open Source C++ Heterogeneous-compute Interface for Portability and Efficiency
|14:10||Evaluating Directive-based Programming Models on Wave Propagation Kernels
S. Rodriguez* (Barcelona Supercomputing Center)
|14:35||Performance Portability for GPU Application using High-level Programming Approaches
F. Courteille* (NVIDIA), I. Said (NVIDIA)